Systems on a chip (SOC) typically have a large circuit scale. In a memory circuit built in a semiconductor device such as an SOC, an abrupt power supply variation in association with operations of a logic circuit included in the semiconductor device may result in a latch-up state. In the latch-up state, a semiconductor element in the memory circuit may experience a loss of control while remaining in the on-state. It may thus be necessary to verify on the basis of design data whether there is a possibility that latch-up will occur.
One such verification tool may be a circuit simulation device capable of predicting the occurrence of latch-up and the point of occurrence. This circuit simulation device may extract a portion where latch-up will possibly occur, as a latch-up element from a layout diagram, and generate circuit connection information including connection information in terms of circuitry of the latch-up element. Then, the circuit simulation device may carry out a simulation for a semiconductor integrated circuit including the extracted latch-up element as one circuit element, so that it is predicted whether latch-up will occur in the latch-up element.
Additionally, there may be a method for measurement of the pulse withstand current of a diode using a pulse current application scheme that is simple and in which conditions may be changed. In the method for measurement of the pulse withstand current, an IC package including a p-n junction diode intentionally built in parallel to an output MOS transistor of the main body of the IC package or a p-n junction diode that is parasitic in the main body of the IC package is used. The IC package may apply a forward voltage to the p-n junction diode on the basis of change in the reference potential under control of the output MOS transistor and thereby forcibly turn on a parasitic transistor that is parasitic in the main body of the IC package, so that a pulse current Iout is generated. The method for measurement of the pulse withstand current mentioned above may pass a pulse current Iin through the p-n junction diode while fixing the output MOS transistor to the on state so as to maintain the parasitic transistor in such a state that the parasitic transistor is forcibly turned on, and may change a continuous current It for pressure testing and pass it through the parasitic transistor, thereby measuring the limiting current of the parasitic transistor.
Additionally, there may be a method for evaluating noise resistance of a semiconductor integrated circuit. In this method, noise resistance of the semiconductor integrated circuit may be evaluated by analyzing the transmission path of noise and the impedance of the path.
Japanese Laid-open Patent Publication No. 10-135335, Japanese Laid-open Patent Publication No. 2001-296327, and Japanese Laid-open Patent Publication No. 2012-089107 are examples of the related art.